Development of a Generator for PCB Footprints from ASIC Layout Data

ASICs developed at IMMS are often built using a chip-on-board process in which the chips are glued onto standard PCBs and connected via bonding wires or bonding balls. In order to design the necessary PCBs, a suitable footprint and the corresponding symbol must be drawn in the PCB software (usually Altium Designer). There is currently no automated export from the ASIC design environment (Cadence Virtuoso), so the data exchange takes place via manually created drawings and pin lists.
This process carries a risk of human error, e.g. mirrored footprints or incorrect assignment of pins, which require a redesign of the PCBs and result in additional costs and delays.
The goal of this internship is to develop a Python-based tool that takes over the process and prevents such errors. For this purpose, the layout data is to be imported in a standardized format (e.g. GDSII) and the position and name of the pads are to be extracted. A footprint and symbol should then be generated for Altium.
In order to adapt the tool to different bonding processes and PCB manufacturers, the footprint generator must offer configuration and modular expansion. In addition, detailed logs must be generated to document the steps performed by the tool and to detect possible errors.

• Get familiar with the layout data format, develop an algorithm for extracting pad positions and pin names
• Research possibilities for Python-based generation of components (footprint and symbol) for Altium or in a universal format
• Implement two generators for solder ball process (PCB pads directly below ASIC pads) and wire bond process (PCB pads in one or more strips next to the ASIC pads) and the associated symbol
• Combine the developed processes in an application (e.g. as a command line program), including generation of logs for documentation purposes
• Document the results