Student (m/f/d): Netlist Carpentry: Automatic Constraint Annotation for digital circuits

The optimization of digital circuits is a central process in hardware development. At IMMS, the open-source Python framework “Netlist Carpentry” was developed for this purpose. It automatically analyzes and modifies netlists to save area or power, for example. This requires that boundary constraints are met, such as timing constraints. The timing constraints of a design (e.g. the maximum allowable delays of individual signal paths) are typically stored in the SDC format (Synthesis Design Constraints). To enable Netlist Carpentry to verify compliance with the constraints itself or to use them in other ways, the constraints must be read in and annotated within the design, for example, on individual gates or the circuit as a whole. This requires an SDC parser. This thesis will therefore involve investigating existing SDC parsing libraries and, if necessary, implementing a custom parser. The imported constraints must then be annotated in the circuit in a meaningful way. The entire process must be documented and verified through testing.

• Familiarization with the structure of Netlist Carpentry
• Investigation whether applicable SDC parsing libraries exist
• Connection of a matching SDC library to Netlist Carpentry or implementation of an SDC parser
• Design und successive implementation of a process that interprets given SDC commands and annotates them onto a circuit in a meaningful manner
• Documentation, Test and Evaluation of the created and implemented annotation process