Technology Mapping of Digital Circuits

State-of-the-art Digital circuits are designed as a behavioral description in e.g. Verilog, which are then transformed into gate network lists and later layouts. An important part of this process is the mapping of the logic equations to the standard cells. These standard cells available in the technology (i.e. logic gates). In this step, both logic equations and logic gates are represented as and-inverter graphs. This allows the process to be reduced to a pattern matching of graphs. The ABC tool from Berkeley, for example, is used for this purpose (https://people.eecs.berkeley.edu/~alanmi/abc/), which, however, has some technical deficits and is difficult to customise due to its difficult to customise due to its structure. For this reason, this thesis will develop its own technology mapping tool based on Python, which realises this process. realises this process. Firstly, suitable interfaces to existing tools (e.g. Yosys) that allow the use of digital and mixed-signal components.

This data is to be read into Python and processed with the NetworkX library, which provides the necessary graph algorithms.

• Definition of software structure and required interfaces
• Implementation of the interfaces
• Realisation of a simple technology-mapping algorithm
• Export the data to Verilog
• Benchmarking and Doc