Machine learning based prediction of critical paths in digital circuits

The design of digital circuits and systems is similar to software design: The behavior of the target circuit is described by means of source code in a hardware description language. This description is afterwards translated, synthesized in boolean logic and finally to a chip layout or FPGA bitstream.

Still, the maximum clock frequency/speed, the area or ressource usage and the power consumption can only be predicted after this lengthy synthesis process. Especially in systems requiring high clock frequencies, this often leads to design iterations if the target speed cannot be met, i.e. the logic get too long. The emerging critical paths have therefore tob e found in the code and relaxed or refactored. If the overall synthesis time is in range of hours or day (which is quite common), this process causes a lot of effort and delay.

This thesis aims at estimating the critical paths in a very early stage in the design process. The code should be analyzed by the free synthesis tool yosys resulting in a (data-flow) graph representation. This graph is then to be rated using a machine learning algorithm to make the critical paths visible in the code. For generating the training data, the commercial synthesis processes are available and can be used.

Finally, a tool for the automated processing of verilog code is to be created.

• Conceptual design of the machine learning algorithm
• Generation of training data with the existing flow based on open hardware designs
• Realization, training and evaluation of the machine learning system
• Documentation